EP1K10TC144-1N

Product Summary

The EP1K10TC144-1N is a Programmable logic device. It provides a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. Based on reconfigurable CMOS SRAM elements, the EP1K10TC144-1N architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components. The advanced process and the low voltage requirement of the 2.5-V core allow the EP1K10TC144-1N to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches.

Parametrics

EP1K10TC144-1N absolute maximum ratings: (1)Supply voltage:–0.5 to 3.6V or–0.5 to 4.6V; (2)DC input voltage:–2.0 to 5.75V; (3)DC output current, per pin:–25 to 25mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:135℃.

Features

EP1K10TC144-1N features: (1)Individual tri-state output enable control for each pin; (2)Open-drain option on each I/O pin; (3)Programmable output slew-rate control to reduce switching noise; (4)Clamp to VCCIO user-selectable on a pin-by-pin basis; (5)Supports hot-socketing; (6)FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays; (7)Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions); (8)Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions); (9)Tri-state emulation that implements internal tri-state buses; (10)Up to six global clock signals and four global clear signals; (11)Cost-optimized process; (12)Low cost solution for high-performance communications applications; (13)Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions ; (14)Dual-port capability with up to 16-bit width per embedded array block (EAB); (15)Logic array for general logic functions.

Diagrams