(China (Mainland))
Product Summary
The H5DU2562GTR-E3C is a 268, 435, 456-bit CMOS Double Data Rate (DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The H5DU2562GTR-E3C offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK) , Data,Data strobes and Write data masks inputs are sampled on both rising and falling edges of the H5DU2562GTR-E3C .
Parametrics
H5DU2562GTR-E3C absolute maximum ratings: (1) Operating Temperature (Ambient) TA: 0-70°C; (2) Storage Temperature TSTG: -55 to 150°C; (3) DD relative to VSS Voltage on VSS VDD: -1.0 to 3.6V; (4) DDQ relative to VSS
Voltage on VSS: VDDQ: -1.0 to 3.6V; (5) Voltage on inputs relative to VSS VINPUT: -1.0 to 3.6V; (6) Voltage on I/O pins relative to VSS VIO: -0.5 to 3.6V; (7) Output Short Circuit Current IOS: 50mA; (8) Soldering Temperature Time TSOLDER: 260.10°C. Sec.
Features
H5DU2562GTR-E3C features: (1) VDD, VDDQ = 2.5V +/- 0.2V; (2) All inputs and outputs are compatible with SSTL_2interface; (3) Fully differential clock inputs (CK, /CK) operation;(4) Double data rate interface; (5) Source synchronous data transaction aligned tobidirectional data strobe (DQS) (6)x16 device has two bytewide data strobes (UDQS,LDQS) per each x8 I/O; (7) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centeredDQ) ; (8) On chip DLL align DQ and DQS transition with CKtransition; (9) DM mask write data-in at the both rising and fallingedges of the data strobe; (10) All addresses and control inputs except data, datastrobes and data masks latched on the rising edgesof the clock; (11) Programmable CAS latency 2/2.5 (DDR200, 266,333), 3 (DDR400) and 4 (DDR500) supported; (12) Programmable burst length 2/4/8 with both sequen-tial and interleave mode; (13) Internal four bank operations with single pulsed/RAS; (14) Auto refresh and self refresh supported; (15)tRAS lock out function supported; (16) 8192 refresh cycles/64ms; (17) JEDEC standard 400mil 66pin TSOP-II with 0.65mmpin pitch; (18)This product is in compliance with the direc-tive pertaining of RoHS.
Diagrams
