Product Summary

The K4S641632K-UC75 is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097, 152 words by 8bits, 4 x 1, 048, 576 words by 16 bits, fabricated with SAMSUNG high performance CMOS technology. Synchronous design of the K4S641632K-UC75 allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-mance memory system applications.

Parametrics

K4S641632K-UC75 absolute maximum ratings: (1) Voltage on any pin relative to Vss VIN, VOUT: -1.0 to 4.6V; (2) Voltage on VDD supply relative to VSS VDD, VDDQ: -1.0 to 4.6V; (3) Storage temperature TSTG: -55 to +150°C; (4) Power dissipation PD: 1W; (5) Short circuit current IOS: 50mA.

Features

K4S641632K-UC75 features: (1) JEDEC standard 3.3V power supply; (2) LVTTL compatible with multiplexed address; (3)Four banks operation; (4) MRS cycle with address key programs CAS latency (2 & 3) Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) ; (5) All inputs are sampled at the positive going edge of the system clock; (6) Burst read single-bit write operation; (7) DQM (x8) & L(U)DQM (x16) for masking; (8) Auto & self refresh 64ms, refresh period (4K cycle).

Diagrams

K4S641632K-UC75 Functional Block Diagram

K4S640432D
K4S640432D

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Data Sheet

Negotiable 
K4S640432F
K4S640432F

Other


Data Sheet

Negotiable 
K4S640432H-TC(L)75
K4S640432H-TC(L)75

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Data Sheet

Negotiable 
K4S640432H-UC
K4S640432H-UC

Other


Data Sheet

Negotiable 
K4S640832C
K4S640832C

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Data Sheet

Negotiable 
K4S640832D
K4S640832D

Other


Data Sheet

Negotiable