(China (Mainland))
Product Summary
The MT48LC16M16A2P-75IT:D DARM is a high-speed CMOS, dynamicrandom access memory containing 268, 435, 456 bits. The MT48LC16M16A2P-75IT:Dis internally configured as a quad-bank DRAM with a synchronous interface (all signalsare registered on the positive edge of the clock signal,CLK) . The MT48LC16M16A2P-75IT:D uses an internal pipelined architecture to achieve high-speed operation. The MT48LC16M16A2P-75IT:D is designed to operate in 3.3V memory systems.
Parametrics
MT48LC16M16A2P-75IT:D absolute maximum ratings: (1) Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2) Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3) Operating Temperature, TA (commercial) : 0°C to 70°C; (4) Operating Temperature,TA (industrial IT) : -40°C to +85°C; (5) Storage Temperature (plastic): -55°C to +150°C; (6) Power Dissipation: 1W.
Features
MT48LC16M16A2P-75IT:D features: (1) PC66-, PC100-, and PC133-compliant; (2) Fully synchronous; all signals registered on positive edge of system clock; (3) Internal pipelined operation; column address can be changed every clock cycle; (4) Internal banks for hiding row access/precharge; (5) Programmable burst lengths: 1, 2, 4, 8, or full page; (6) Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7) Self Refresh Mode; (8) 64ms, 8,192-cycle refresh; (9) LVTTL-compatible inputs and outputs; (10) Single +3.3V ±0.3V power supply.
Diagrams
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Switchcraft |
Patch Panels PATCHBAY |
Data Sheet |
Negotiable |
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Patch Panels PATCHBAY |
Data Sheet |
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MT48H16M16LF |
Other |
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Data Sheet |
Negotiable |
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Data Sheet |
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MT48H16M16LFBF-6:H |
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Data Sheet |
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MT48H16M16LFBF-75 AT:G TR |
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IC SDRAM 256MBIT 132MHZ 54VFBGA |
Data Sheet |
Negotiable |
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